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cat5241 ? catalyst semiconductor, inc. 1 doc. no. md-2011 rev. n characteristics subject to change without notice quad digitally programmable potentiometer (dpp?) with 64 taps and 2-wire interface features ? four linear-taper digitally programmable potentiometers ? 64 resistor taps per potentiometer ? end to end resistance 2.5k ? , 10k ? , 50k ? or 100k ? ? potentiometer control and memory access via 2-wire interface (i 2 c like) ? low wiper resistance, typically 80 ? ? nonvolatile memory storage for up to four wiper settings for each potentiometer ? automatic recall of saved wiper settings at power up ? 2.5 to 6.0 volt operation ? standby current less than 1a ? 1,000,000 nonvolatile write cycles ? 100 year nonvolatile memory data retention ? 20-lead soic and tssop packages ? industrial temperature range for ordering information details, see page 15. pin configuration soic 20 lead (w) tssop 20 lead (y) r w0 1 20 v cc r l0 2 19 r w3 r h0 3 18 r l3 a0 4 17 r h3 a2 5 16 a1 r w1 6 15 a3 r l1 7 14 scl r h1 8 13 r w2 sda 9 12 r l2 gnd 10 11 r h2 cat 5241 description the cat5241 is four digitally programmable potentiometers (dpps?) integrated with control logic and 16 bytes of nvram memory. each dpp consists of a series of 63 resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper outputs with cmos switches. a separate 6-bit control register (wcr) independently controls the wiper tap switches for each dpp. associated with each wiper control register are four 6-bit non-volatile memory data registers (dr) used for storing up to four wiper settings. writing to t he wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (i 2 c-like). on power-up, the contents of the first data register (dr0 ) for each of the four potentiometers is automatically loaded into its respective wiper control register (wcr). the cat5241 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. functional diagram r w0 r w1 r h0 scl sda a0 a1 a2 a3 r h1 r l0 r l1 nonvolatile data registers wiper control registers control logic 2-wire bus interface r w2 r h2 r l2 r w3 r h3 r l3
cat5241 doc. no. md-2011 rev. n 2 ? catalyst semiconductor, inc. characteristics subject to change without notice pin description pin (soic) name function 1 r w0 wiper terminal for potentiometer 0 2 r l0 low reference terminal for potentiometer 0 3 r h0 high reference terminal for potentiometer 0 4 a0 device address, lsb 5 a2 device address 6 r w1 wiper terminal for potentiometer 1 7 r l1 low reference terminal for potentiometer 1 8 r h1 high reference terminal for potentiometer 1 9 sda serial data input/output 10 gnd ground 11 r h2 high reference terminal for potentiometer 2 12 r l2 low reference terminal for potentiometer 2 13 r w2 wiper terminal for potentiometer 2 14 scl bus serial clock 15 a3 device address 16 a1 device address 17 r h3 high reference terminal for potentiometer 3 18 r l3 low reference terminal for potentiometer 3 19 r w3 wiper terminal for potentiometer 3 20 v cc supply voltage pin description scl: serial clock the cat5241 serial clock input pin is used to clock all data transfers into or out of the device. sda: serial data the cat5241 bidirectional serial data pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-or'd with the other open drain or open collector outputs. a0, a1, a2, a3: device address inputs these inputs set the device address when addressing multiple devices. a total of sixteen devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5241. r h , r l : resistor end points the four sets of r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the four r w pins are equivalent to the wiper terminal of a mechanical potentiometer. device operation the cat5241 is four resistor arrays integrated with 2- wire serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. each resistor array contains 63 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resis? tors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. also, the device c an be instructed to operate in an "increment/decrement" mode.
cat5241 ? catalyst semiconductor, inc. 3 doc. no. md-2011 rev. n characteristics subject to change without notice absolute maximum ratings (1) parameter ratings units temperature under bias -55 to +125 c storage temperature -65 to +150 c voltage on any pin with respect to v ss (2)(3) -2.0 to +v cc +2.0 v v cc with respect to ground -2.0 to +7.0 v package power dissipation capability (t a = 25c) 1.0 w lead soldering temperature (10s) 300 c wiper current 12 ma recommended operating conditions v cc = +2.5v to +6v parameter ratings units operating ambient temperature (industrial) -40 to +85 c potentiometer characteristics over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ max units r pot potentiometer resistance (-00) 100 k ? r pot potentiometer resistance (-50) 50 k ? r pot potentiometer resistance (-10) 10 k ? r pot potentiometer resistance (-25) 2.5 k ? potentiometer resistance tolerance 20 % r pot matching 1 % power rating 25c, each pot 50 mw i w wiper current 6 ma r w wiper resistance i w = 3ma @ v cc =3v 300 ? r w wiper resistance i w = 3ma @ v cc = 5v 80 150 ? v term voltage on any r h or r l pin v ss = 0v gnd v cc v n noise (4) tbd nv/ hz resolution 1.6 % absolute linearity (5) r w(n)(actual) - r (n)(expected) (8) 1 lsb (7) relative linearity (6) r w(n+1) - [r w(n)+lsb ] (8) 0.2 lsb (7) tc rpot temperature coefficient of r pot (4) 300 ppm/c tc ratio ratiometric temp. coefficient (4) 20 ppm/c c h /c l /c w potentiometer capacitances (4) 10/10/25 pf fc frequency response r pot = 50k ? (4) 0.4 mhz notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2.0v for periods of less than 20ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20ns. (3) latch-up protection is provided for stresses up to 100ma on address and data pins from ?1v to v cc + 1v. (4) this parameter is tested initially and after a des ign or process change that affects the parameter. (5) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position wh en used as a potentiometer. (6) relative linearity is utilized to determine the actual c hange in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (7) lsb = r tot / 63 or (r h - r l ) / 63, single pot (8) n = 0, 1, 2, ..., 63
cat5241 doc. no. md-2011 rev. n 4 ? catalyst semiconductor, inc. characteristics subject to change without notice d.c. operating characteristics over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ max units i cc power supply current f scl = 400khz 1 ma i sb standby current (v cc = 5.0v) v in = gnd or v cc ; sda = gnd; r wx = gnd (2) 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) i ol = 3 ma 0.4 v capacitance t a = 25c, f = 1.0mhz, v cc = 5v symbol parameter test conditions min typ max units c i/o (1) input/output capacitance (sda) v i/o = 0v 8 pf c in (1) input capacitance (a0, a1, a2, a3, scl) v in = 0v 6 pf a.c. characteristics over recommended operating conditi ons unless otherwise stated. symbol parameter min typ max units f scl clock frequency 400 khz t i (1) noise suppression time constant at scl, sda inputs 50 ns t aa slc low to sda data out and ack out 0.9 s t buf (1) time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setup time (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 ns t su:dat data in setup time 100 ns t r (1) sda and scl rise time 0.3 s t f (1) sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 50 ns power up timing (1) over recommended operating conditi ons unless otherwise stated. symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms note: (1) this parameter is tested initially and after a des ign or process change that affects the parameter. (2) all four wiper terminals r w0 , r w1 , r w2 , and r w3 are tied to ground.
cat5241 ? catalyst semiconductor, inc. 5 doc. no. md-2011 rev. n characteristics subject to change without notice write cycle limits over recommended operating conditi ons unless otherwise stated. symbol parameter min typ max units t wr write cycle time 5 ms the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. reliability characteristics over recommended operating conditi ons unless otherwise stated. symbol parameter reference test method min typ max units n end (1) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (1) data retention mil-std-883, test method 1008 100 years v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma note: (1) this parameter is tested initially and after a des ign or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. figure 1. bus timing figure 2. write cycle timing figure 3. start/stop timing t wr stop condition start condition address ack 8th bit byte n scl sda start bit sda stop bit scl t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat5241 doc. no. md-2011 rev. n 6 ? catalyst semiconductor, inc. characteristics subject to change without notice serial bus protocol the following defines the f eatures of the 2-wire bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5241 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5241 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 0101 for the cat5241 (see figure 5). the next four significant bits (a3, a2, a1, a0) are the device address bits and define which device the master is accessing. up to sixteen devices may be individually addressed by the system. typically, +5v and ground are hard-wired to these pins to establish the device's address. after the master sends a start condition and the slave address byte, the ca t5241 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signa ling that it received the 8 bits of data. the cat5241 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat5241 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5241 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. figure 4. acknowledge timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat5241 ? catalyst semiconductor, inc. 7 doc. no. md-2011 rev. n characteristics subject to change without notice write operation in the write mode, the master device sends the start condition and the slave address information to the slave device. after the slave generates an acknowledge, the master se nds the instruction byte that defines the requested operation of cat5241. the instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. after receiving another acknowledge from the slave, the master device transmits the data to be written into the selected register. the cat5241 acknowledges once more and the master generates the stop condition, at which time if a non-volatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the cat5241 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave addres s. if the cat5241 is still busy with the write operation, no ack will be returned. if the cat5241 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation. figure 5. slave address bits cat5241 0 1 0 1 a3 a2 a1 a0 * a0, a1, a2 and a3 correspond to pin a0, a1, a2 and a3 of the device. ** a0, a1, a2 and a3 must compare to its corresponding hard wired input pins. figure 6. write timing s a c k a c k dr wcr data s t o p p bus activity: master sda line s t a r t a c k slave/dpp address instruction byte fixed variable op code data register address pot/wcr address
cat5241 doc. no. md-2011 rev. n 8 ? catalyst semiconductor, inc. characteristics subject to change without notice instructions and register description slave address byte the first byte sent to the cat5241 from the master/processor is called the slave/dpp address byte. the most significant four bits of the slave address are a device type ident ifier. these bits for the cat5241 are fixed at 0101[b] (refer to table 1). the next four bits, a3 - a0, are the internal slave address and must match the physical device address which is defined by the state of the a3 - a0 input pins for the cat5241 to successfully continue the com- mand sequence. only the device which slave address matches the incoming device address sent by the master executes the instruct ion. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte the next byte sent to the cat5241 contains the instruction and register poin ter information. the four most significant bits used provide the instruction opcode i [3:0]. the p1 and p0 bits point to one of four wiper control registers. the least two significant bits, r1 and r0, point to one of t he four data registers of each associated potentiometer. the format is shown in table 2. data register selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 table 1. identification byte format table 2. instruction byte format id3 id2 id1 id0 a3 a2 a1 a0 0101 (msb) (lsb) device type identifier slave address i3 i2 i1 i0 r1 r0 p1 p0 (msb) (lsb) instruction data register wcr/pot selection opcode selection
cat5241 ? catalyst semiconductor, inc. 9 doc. no. md-2011 rev. n characteristics subject to change without notice wiper control and data registers wiper control register (wcr) the cat5241 contains four 6-bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 64 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via write wiper contro l register instruction; it may be written by transferri ng the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of it s data register zero (dr0) upon power-up. the wiper control register is a volatile register that loses its contents when the cat5241 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers (dr) each potentiometer has four 6-bit non-volatile data registers. these can be read or written directly by the host. data can also be tran sferred between any of the four data registers and the associated wiper control register. any data changes in one of the data regis? ters is a non-volatile operation and will take a maximum of 5ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as standard memory locations for system parameters or user preference data. instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper control register ? read the current wiper position of the selected potentiometer in the wcr ? write wiper control register ? change current wiper position in the wcr of the selected potentiometer ? read data register ? read the contents of the selected data register ? write data register ? write a new value to the selected data register the basic sequence of the three byte instructions is illustrated in figure 8. thes e three-byte instructions table 3. instruction set instruction set instruction i3 i2 i1 i0 wcr1 / p1 wcr0 / p0 r1 r0 operations read wiper control register 1 0 0 1 1/0 1/0 0 0 read the contents of the wiper control register pointed to by p1-p0 write wiper control register 1 0 1 0 1/0 1/0 0 0 write new value to the wiper control register pointed to by p1-p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1-p0 and r1-r0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1-p0 and r1-r0 xfr data register to wiper control register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1-p0 and r1-r0 to its associated wiper control register xfr wiper control register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper control register pointed to by p1-p0 to the data register pointed to by r1-r0 global xfr data registers to wiper control registers 0 0 0 1 0 0 1/0 1/0 transfer the contents of the data registers pointed to by r1-r0 of all four pots to their respective wiper control registers global xfr wiper control registers to data register 1 0 0 0 0 0 1/0 1/0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1-r0 of all four pots increment/decrement wiper control register 0 0 1 0 1/0 1/0 0 0 enable increment/decrement of the control latch pointed to by p1-p0 note: 1/0 = data is one or zero
cat5241 doc. no. md-2011 rev. n 10 ? catalyst semiconductor, inc. characteristics subject to change without notice exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non- volatile memory and takes a maximum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two-byte sequence to complete, as illustrated in fi gure 7. these instructions transfer data between the host/processor and the cat5241; either between t he host and one of the data registers or directly bet ween the host and the wiper control register. these instructions are: ? xfr data register to wiper control register this transfers the content s of one specified data register to the associated wiper control register. ? xfr wiper control register to data register this transfers the content s of the specified wiper control register to the specified associated data register. ? global xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. ? global xfr wiper counter register to data register this transfers the conten ts of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 5 and 9). the increment/decrement command is different from the other commands. once the command is issued and the cat5241 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tu ning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, t he selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 7. two-byte instruction sequence figure 8. three-byte instruction sequence figure 9. increment/decrement instruction sequence s t a r t 0101 a2 a0 a c k i2 i1 i0 r1 r0 a c k sda s t o p id3 id2 id1 id0 device id internal instruction opcode address register address 0 p0 pot/wcr address a1 a3 i3 i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address wcr[7:0] or data register d[7:0] s t a r t 0101 a2 a1 a0 a c k pot/wcr address 0 p0 a c k sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3 i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address s t a r t 0101 a2 a1 a0 a c k r0 pot/wcr address 0p0 a c k sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3
cat5241 ? catalyst semiconductor, inc. 11 doc. no. md-2011 rev. n characteristics subject to change without notice figure 10. increment/decrement timing limits instruction format read wiper control register (wcr) device addresses instruction data s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1001p1p000 a c k 7654 3 2 1 0 a c k s t o p write wiper control register (wcr) device addresses instruction data s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1010p1p000 a c k 7654 3 2 1 0 a c k s t o p read data register (dr) device addresses instruction data s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1 0 1 1 p1 p0 r1 r0 a c k 7 6 5 4 3 2 1 0 a c k s t o p write data register (dr) device addresses instruction data s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1 1 0 0 p1 p0 r1 r0 a c k 7 6 5 4 3 2 1 0 a c k s t o p scl sda r w inc/dec command issued voltage out t wrid
cat5241 doc. no. md-2011 rev. n 12 ? catalyst semiconductor, inc. characteristics subject to change without notice global transfer data register (dr) to wiper control register (wcr) device addresses instruction s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 000100r1r0 a c k s t o p global transfer wiper control register (wcr) to data register (dr) device addresses instruction s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 100000r1r0 a c k s t o p transfer wiper control register (wcr) to data register (dr) device addresses instruction s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1 1 1 0 p1 p0 r1 r0 a c k s t o p transfer data register (dr) to wiper control register (wcr) device addresses instruction s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 1 1 0 1 p1 p0 r1 r0 a c k s t o p increment (i)/decrement (d) wi per control register (wcr) device addresses instruction data s t a r t 0 1 0 1 a3 a2 a1 a0 a c k 0 0 1 0p1p00 0 a c k i/d i/d . . . i/d i/d a c k s t o p notes: (1) any write or transfer to the non-volatile data registers is followed by a high voltage cycle after a stop has been issued.
cat5241 ? catalyst semiconductor, inc. 13 doc. no. md-2011 rev. n characteristics subject to change without notice package outline drawings soic 20-lead 300 mils (w) (1)(2) notes: (1) all dimensions are in millimeters. angles in degree. (2) complies with jedec standard ms-013. 2hfor current tape and reel information, download the pdf file from: a2 e1 e a1 e pin#1 identification b d c a top view side view end view 1 1 h h l symbol min nom max a 2.36 2.49 2.64 a1 0.10 0.30 a2 2.05 2.55 b 0.31 0.41 0.51 c 0.20 0.27 0.33 d 12.60 12.80 13.00 e 10.01 10.30 10.64 e1 7.40 7.50 7.60 e1.27 bsc h0.25 0.75 l 0.40 0.81 1.27 0 8 15 15
cat5241 doc. no. md-2011 rev. n 14 ? catalyst semiconductor, inc. characteristics subject to change without notice tssop 20-lead 4.4mm (y) (1)(2) notes: (1) all dimensions are in millimeters. angles in degree. (2) complies with jedec standard m0-153. 1 a1 a2 d top view side view end view e e1 e b l c l1 a symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 1.05 b0.19 0.30 c0.09 0.20 d 6.40 6.50 6.60 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 10 8 4hfor current tape and reel information, download the pdf file from:
cat5241 ? catalyst semiconductor, inc. 15 doc. no. md-2011 rev. n characteristics subject to change without notice example of ordering information notes: (1) all packages are rohs compliant (lead-free, halogen-free). (2) standard lead finish is matte-tin. (3) this device used in the above example is a cat5241wi-10-t1 (soic, industrial temperature, 10k ? , tape & reel). ordering part number cat5241wi-25 cat5241wi-10 cat5241wi-50 cat5241wi-00 cat5241yi-25 cat5241yi-10 cat5241yi-50 cat5241yi-00 prefix device # suffix cat 5241 w i -10 t1 optional company id package w: soic y: tssop temperature range i = in dustrial (- 40oc to 85oc) product number 5241 tape & reel t: tape & reel 1: 1000/reel resistance -25: 2.5k ? -10: 10k ? -50: 50k ? -00: 100k ?
revision history date rev. reason 09/30/2003 g deleted wp from functional diagram, pg. 1 03/03/2004 h added tssop package in all areas 03/29/2004 i eliminated data sheet designation eliminated commercial temperature range in all areas updated absolute max ratings and potentiometer characteristics notes 04/05/2004 j corrected potentiometer resist ance [changed (-2.5) to (-25)] in table 04/22/2006 k updated example of ordering information 05/24/2007 l updated 20-lead tssop package drawing updated example of ordering information update copyrights, trademarks and patents added md- in front of document no. 06/20/2007 m update pin description update d.c operating characteristic s: standby current test conditions 02/04/2008 n update package outline drawings catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: md-2011 fax: 408.542.1200 revision: n 1hwww.catsemi.com issue date: 02/04/08 copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and register ed trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quant um charge programmable? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or guar antee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or se rvice described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

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